1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a rewrite data setting function (i.e. a verify function), and more particularly to a sense amplifier type circuit used for write and read operations.
2. Description of the Related Art
Since a non-volatile semiconductor memory device has an advantage in which data is not lost even if power is turned off, a demand for such non-volatile semiconductor memories has recently increased more and more. Unlike a two-transistor byte-type non-volatile semiconductor memory device, a flash memory or an electrically batch-erasable non-volatile semiconductor memory device may have a memory cell constituted by a single transistor. As a result, the size of the memory cell can be decreased, and it is expected to substitute the flash memory for a large-capacity magnetic disk.
In this type of non-volatile semiconductor memory device, a memory cell array is constituted by arranging memory cells comprising MOS transistors with floating gates in a matrix. A threshold value of the MOS transistor is varied by accumulating a charge in the floating gate, and data is stored by the threshold value. At the time of data write or data read, an electric current is let to flow to the gate insulative film to control data. Thus, a write time varies greatly, depending on a change in process or use condition. This is a principal difference between the above non-volatile semiconductor memory device and a DRAM or SRAM. As a result, a single chip may comprise cells with a short write time and cells with a long write time.
In order to describe the above problems in detail, a conventional non-volatile semiconductor memory device with reference to a NAND type flash memory.
FIG. 1 is a circuit diagram showing a cell structure of the NAND type flash memory. Non-volatile memory cells M1 to M16, each comprising a MOS transistor having a floating gate, are connected in series. The memory cell M1 at one end of the group of the memory cells M1 to M16 is connected to a bit line BL via a selector transistor Q1, and the memory cell M16 at the other end thereof is connected to a common source line S via a selector transistor Q2. Each transistor constituting each cell is formed on a single well substrate W. Control gates of memory cells M1 to M16 are connected to word lines WL1 to WL16, a control electrode of the selector transistor Q1 is connected to a selector line SL1, and a control gate of the selector transistor Q2 is connected to a selector line SL2.
Each of the memory cells M1 to M16 has a threshold value corresponding to data to be stored. When "0" data is stored, the threshold value is set at more than 0 V and less than 5 V. When "1" data is stored, the threshold value is set at less than 0 V. (More appropriately, these threshold values are set in narrow ranges in order to provide some margin.)
FIG. 2 is a graph illustrating a threshold distribution of an N-number of memory cells having threshold values corresponding to the above data "0" and "1". In the case of a NAND type flash memory, the state in which "1" data is stored is normally called "erase state", and the state in which "0" data is stored is called "write state". An operation of shifting the threshold value of a memory cell storing "1" data in a positive direction so that the memory cell may store "0" data is called "write operation". An operation of shifting the threshold value (Vth) of a memory cell storing "0" data in a negative direction so that the memory cell may store "1" data is called "erase operation". This definition of operations may differ in the case of NOR type memory devices.
FIG. 3 is a table showing voltages to be applied to the memory cells at the time of erase and write operations. In the read operation, the bit line BL is precharged at 5 V in a floating state. Then, 5 V is applied to the selector line SL1, 0 V is applied to the word line WL of the selected memory cell, 5 V is applied to the word lines WL of the non-selected memory cells, 5 V is applied to the selector line SL2, 0 V is applied to the well substrate W, and 0 V is applied to the common source line S. Thus, the transistors of all non-selected memory cells, other than the selected memory cell, are turned on. When "0" data is stored in the selected memory cell, this memory cell is in the non-conductive state and the bit line potential remains at 5 V. If "1" data is stored in the selected memory cell, this memory cell is in the conductive state and the bit line potential is discharged and dropped. A data sense operation is effected by sensing the bit line potential at the time of read-out.
FIGS. 4, 5A and 5B show distributions of thresholds of memory cells at the time of erase and write operations. In the erase operation, the bit line BL is opened, 0 V is applied to the selector line SL1, 0 V is applied to the word line WL of the memory cell, 0 V is applied to the selector line SL2, 18 V is applied to the well substrate W, and 18 V is applied to the common source line S. Thus, a tunnel current flows across the floating gate and the well via the gate insulative film, and the threshold value lowers to 0 V or less. FIG. 4 shows a shift of the threshold value distribution.
At the time of the write operation, different voltages are applied in accordance with write data. Specifically, in the case of "0" data write (i.e. in the case of shifting the threshold value), 0 V is applied to the bit line BL. In the case of "1" data write (i.e. in the case of not shifting the threshold value), 9 V is applied to the bit line BL. A potential of 11 V is applied to the selector line SL1, 18 V is applied to the word line WL of the selected memory cell, 9 V is applied to the word line WL of the non-selected memory cell, 0 V is applied to the selector line SL2, 0 V is applied to the well W, and 0 V is applied to the common source line S. As a result, the selector transistor Q1 and all memory cells M1 to M16 are turned on and set at the same potential as the bit line potential (no consideration is given to a drop in threshold value of transistors). Accordingly, in the memory cell in which 0 V is applied to the bit line BL, a high voltage of 18 V is applied between the channel and the control electrode, a tunnel current flows, and the threshold value shifts to the positive side. On the other hand, in the memory cell in which 9 V is applied to the bit line BL, only 9 V is applied between the channel and the control electrode. Thus, the threshold value is not shifted to the positive side. This "9 V" is called "write prohibition voltage". FIGS. 5A and 5B illustrate the shift of distribution of these threshold values.
As stated above, in the non-volatile semiconductor device, a write operation is effected by using purely physical means of a tunnel current (Fowler-Nordheim tunneling). Thus, the write speed varies from memory cell to memory cell. Even if the same write time is set, a threshold value of a certain memory cell may fall within a range of 0 V to 5 V, but a threshold value of another memory cell may exceed 5 V. This phenomenon is illustrated in FIG. 6.
Specifically, "0" data is written in a cell with low write speed at time t1. However, when "0" data is written in a cell with high write speed, the threshold voltage has exceeded 5 V which is an upper limit value. As described above, at the time of read-out of the NAND type flash memory, 5 V is applied to the word line of the non-selected memory cell to turn on the word line. If the threshold of a certain memory cell exceeds 5 V, data in all memory cells connected in series to this memory cell cannot be read out because the series current path is cut off.
It is therefore necessary to narrow the distribution of thresholds to a predetermined value range. In order to keep a sufficient read-out margin, it is desirable to narrow this distribution to a smaller range.
A bit-by bit verify method has been proposed to solve this problem. According to this method, the write time is not made constant for all memory cells, unlike the above-described technique, and different write times are set for the respective memory cells. In principle, the write time is divided into short time periods, and the following steps are repeated: write.fwdarw.verify.fwdarw.rewrite data set.fwdarw.write.fwdarw.verify.fwdarw.rewrite data set . . . . As regards the memory cell the threshold of which has been sufficiently increased by the verify operation, the rewrite data is set so as to prevent the write operation in the next cycle.
Thus, the cell with high write speed completes the write operation earlier, and the threshold thereof will not increase afterwards (in this case, an increase in threshold due to a potential difference of 9 V is ignored). FIG. 7 illustrates this technique. The cell with high write speed completes the write operation at time t0, and the cell with low write speed completes the write operation at time t1. The threshold values are set near 3.5 V.
The bit-by-bit verify method can be realized most easily by making use of an external system such as a CPU or software. However, in the NAND type flash memory wherein several-thousand bits are written simultaneously, it is not practical to input/output several-thousand bit data by using an I/O interface of 8 bits at most in each verify operation. In addition, a several-thousand bit register or comparator needs to be provided externally. Accordingly, it is most desirable to perform the verify operation and rewrite data set operation within the chip.
In a most primitive method for achieving the bit-by-bit verify, it will suffice to provide only the same number of flip-flop circuits for latching write data, flip-flop circuits for latching read-out data and comparators for comparing both write data and read-out data as the number of bit lines (several thousand). However, this is impractical.
FIG. 8 shows schematically a circuit for achieving the bit-by-bit verify operation within the chip. This circuit comprises flip-flop circuits 1 (1-x; x=1-3) for temporarily storing write data; bit lines BL (BLx; x=1-3); NAND type memory cells 2 (2-x; x=1-3), as illustrated in FIG. 1, connected to the bit lines BL; P-channel transistors Q3 for charging the bit lines BL; N-channel transistors Q4 for connecting the bit lines BL and flip-flops 1; and N-channel transistors Q5 and Q6 connected in series between a power supply potential of 5 V and the bit lines BL. The gates of transistors Q5 are connected to bit-line-side terminals of the flip-flops 1.
For the purpose of simplicity, FIG. 8 shows the circuit corresponding to only three bit lines, but in fact there are several thousand bit lines. A signal line .phi.1 is connected to the gates of all transistors Q3, a signal line .phi.2 is connected to the gates of all transistors Q6, and a signal line .phi.3 is connected to the gates of all transistors Q4. The sources of the transistors Q3 are connected to a power supply having a potential of 9 V at the time of write and a potential of 5 V at the other time. In addition, a power supply for the flip-flop circuits has a potential of 9 V at the time of write and a potential of 5 V at the other time.
The operation of the circuit shown in FIG. 8 will now be described with reference to FIG. 9 showing waveforms at the time of the write operation. Suppose that "0" data is written in the memory cell 2-1, "0" data in the memory cell 2-2, and "1" data in the memory cell 2-3, and that data is written less easily in the memory cell 2-2 than in the memory cell 2-1.
At first, write data supplied from the outside via column gates (not shown) is latched in the respective the flip-flop circuits 1. Specifically, a bit-line-side node N1 of the flip-flop circuit 1-1 is set at 0 V, a bit-line-side node N2 of the flip-flop circuit 1-2 is set at 0 V, and a bit-line-side node N3 of the flip-flop circuit 1-3 is set at 5 V. In this state, a first write operation (WRITE-1) starts.
At time t10, when the signal line .phi.1 is set at 0 V, the transistors Q3 are rendered conductive and the bit lines BL are charged at 9 V. Since the power supply for the flip-flop circuits rises to 9 V, the node N3 has a potential of 9 V.
At time t11, the potential of signal line .phi.1 rises to 10 V, and the charge of the bit lines is completed.
At the same time, the potential of signal line .phi.3 rises to 10 V, and the bit lines are discharged according to the potentials of nodes N (Nx; x=1-3). Specifically, since the potentials of nodes N1 and N2 are 0 V, the bit lines BL1 and BL2 are discharged to 0 V. Since the potential of node N3 is 9 V, the bit line BL3 is discharged to 9 V. This potential of 9 V functions as a write prohibition potential for the memory cell 2-3. Under this condition, a write voltage is applied to each memory cell 2.
At time t12, the first write operation is completed, and a verify operation and a rewrite data set operation ("VERIFY") start. The potential of the signal line .phi.1 falls to 0 V, and the bit lines are charged at 5 V via the transistors .phi.3. At the same time, since the potential of the signal line .phi.3 falls to 0 V, the bit lines BL are electrically disconnected from the flip-flop circuits 1.
At time t13, the charging for the bit lines is completed, and the bit lines in the floating state are discharged by the memory cells. The discharge speed varies depending on the threshold values of the memory cells. If the write operation is not fully effected, the threshold value does not rise and the bit line is discharged. In the first write operation, the write operation is not fully effected in either the memory cell 2-1 or memory cell 2-2. Since the write operation for the memory cell 2-3 is not effected, the bit line is necessarily discharged.
At time t14, the potential of the signal line .phi.2 rises to 5 V. Then, all transistors Q6 are turned on. Since the potentials of nodes N1 and N2 are 0 V, the corresponding transistors Q5 are non-conductive and the bit lines BL1 and BL2 are not influenced. Since the potential of node N3 is 5 V, the bit line BL3 is connected to a power supply potential of 5 V via the transistors Q5 and Q6. As a result, the bit line BL3 is charged to 5 V. This operation is referred to as "recharging of bit line of `0` data write cell."
At time t15, the signal line .phi.3 rises to 5 V, the bit lines are connected to the flip-flop circuits, and the bit line potentials are latched in the flip-flop circuits. The potentials latched at the nodes N1 to N3 of flip-flop circuits 1 are 0 V, 0 V and 5 V, respectively, from the uppermost node N1. This state remains the same as before the write operation.
At time t20, a second write operation (WRITE-2) starts. Specifically, 9 V-charging of the bit lines is effected between time t20 and time t21, and data write is effected in the memory cells between time t21 and time t22.
At time t22, second verify and rewrite data set operations are performed. Specifically, 5 V-charging of the bit lines is effected between time t22 and time t23, discharge of the bit lines by the memory cells 2 is effected between time t23 and time t24, and re-charging of the bit lines of "0" write cells is stated from time t24. It should be noted that the potential of the bit line BL1 does not substantially decrease from 5 V. This indicates that the data write in the memory cell 2-1 has been completed.
At time t25, the bit lines are connected to the flip-flop circuits, and the bit line potentials are latched in the flip-flop circuits 1. The potentials latched in the nodes N1 to N3 of the flip-flop circuits are 5 V, 0 V, and 5 V, respectively, from the uppermost node. It should be noted that the potential of the node N1 has changed to 5 V from 0 V in the first operation.
The bits in which write is completed are reset from 0 V to 5 V, and this 5 V is raised to function as 9 V-write prohibition voltage. Thus, no further write operations are effected in these bits.
At time t30, a third write operation (WRITE-3) starts. Specifically, 9 V-charging of the bit lines is effected between time t30 and time t31, and write in memory cells is effected between time t31 and time t32. It should be noted that the potential of the bit line BL1 is 9 V. This 9 V is the same write prohibition voltage as for the bit line BL3.
At time t32, third verify and rewrite data set operations are performed. Specifically, 5 V-charging of the bit lines is effected between time t32 and time t33, discharge of the bit lines by the memory cells 2 is effected between time t33 and time t34, and re-charging of the bit lines of "0" write cells is started from time t34. It should be noted that the potential of the bit line BL2 does not substantially decrease from 5 V. This indicates that the data write in the memory cell 2-2 has been completed.
At time t35, the bit lines are connected to the flip-flop circuits, and the bit line potentials are latched in the flip-flop circuits 1. The potentials latched at the nodes N1 to N3 of the flip-flop circuits are 5 V, 5 V and 5 V, respectively, from the uppermost node. It should be noted that the potential of node N2 has changed to 5 V from 0 V in the second operation. Thus, all (three bits) write operations have been completed.
The operation of the bit-by-bit verify circuit has been described, on the supposition of the ideal case (no interference between adjacent bit lines). This circuit, however, has a serious problem, i.e. a malfunction occurs in the verify operation due to interference between adjacent bit lines. This problem will now be described.
FIG. 10 shows realistic waveforms on the bit lines BL2 and LB3 between time t12 and time t15 in FIG. 9. At time t12, the verify and rewrite data set operations start. The bit lines BL2 and BL3 are charged to 5 V via the transistors Q3. Subsequently, charging of the bit lines is completed at time t13, and the bit lines in the floating state are discharged by the memory cells. The write in the memory cell 2-2 is not fully effected, the threshold value does not rise and the bit line BL2 is discharged. The bit line BL3 is necessarily discharged.
At time t14, the recharging of the bit lines of "0" write cells is performed. Specifically, the bit line BL3 is connected to the power supply potential of 5 V via the transistors Q5 and Q6. As a result, the bit line BL3 is charged to 5 V.
In the meantime, the bit lines extend from end to end of the memory cell array, and the capacitance between adjacent bit lines is not negligible. Thus, as shown in FIG. 11, floating capacitances C1 and C2 occur parasitically. Consequently, when the bit line BL3 is recharged, the potential of the bit line BL2 will rise due to coupling of capacitance. If the bit line BL2 is sensed in this state, distinction between the write-completed bit and write-incomplete bit becomes unclear. As a result, the potential of node N of the corresponding flip-flop circuit may be increased to 5 V, although the write operation is not completed, and the subsequent write operation may be disabled.
In order to overcome the above problem, a verify method called "bit line leaking method" has been proposed. According to this method, over the entire verify operation time (time t12 to time t15), the potential of the signal line .phi.2 is raised to render the transistors Q6 conductive. Thus, the bit line BL3 retains a potential of 5 V from the beginning, and no abrupt change in potential occurs due to recharging.
Accordingly, no malfunction occurs due to interference between the bit lines. However, since the electric current is kept flowing through the conductive cell (memory cell 2-3), power consumption increases. Moreover, since the bit line potential at the time the current is kept flowing is determined by division of resistance between the transistors Q5 and Q6 and memory cell 2-3, the bit line potential cannot perfectly be maintained at 5 V and it is stabilized at a predetermined potential below 5 V. Thus, recharging cannot be avoided and the same problem as stated above will occur. Furthermore, the source potential floats due to the leak current of the bit line, and the read-out margin of the read-out cell lowers.